
INSTRUCTIONS ON BUILDING A RELOADABLE BITSTREAM FOR THE TS-4800

1) You will need to install both Lattice Diamond IDE and Lattice ispVM
standalone programming utility.

2) Make any desired changes to the verilog files.  The simplest changes
are to enable and disable optional cores using the parameters in ts4800_top.v.
Modifying the p_submodel parameter in syscon.v is also recommended.  This is a
4 bit hexadecimal "sub-model" ID code that will allow easy software
confirmation that your changes took effect.

3) Open the project in Lattice Diamond. On the "Process" tab, right-click oni
"Place and Route Trace" and select "Run."  It will take several minutes to
synthesize, map, and place and route the design.  When it finishes, make sure 
the report indicates FREQUENCY contraints are met.  Other contraints are 
over-constrained and failure to meet them is not a problem.

4) Right-click on "JEDEC File" and select "Run."  This should create the file
ts4800/ts4800_ts4800.jed

5) Open ispVM and open ts4800-opencore.xcf.  Click the VME button and click
"Generate".  This will generate a vme file.

6) Compress your bitstream:
gzip -9 ts4800_bitstream.vme

7) Copy your bitstream to the root directory in the fastboot environment on
the TS-4800.  Save the initrd to the boot media with the 'save' command.  Your
new bitstream will now be automatically loaded on each boot.

8) Run 'ts4800ctl --info' and confirm that the submodel value is what you set
it to in verilog.  You are now running a reloaded custom bitstream.

NOTES

- The default linuxrc script on the TS-4800 automatically checks for a file
called /ts4800_bitstream.vme.gz and loads it if it exists.  You must use this
exact name or edit linuxrc accordingly.

- If your application needs to dynamically reload with different bitstreams
without rebooting, please note that this is not supported on the TS-4800.  It
is possible, but any bus cycles emitted by the CPU to FPGA address space
during the reload could hang the board or return invalid data.  If your
application has a touchscreen, then the touchscreen driver will query the
FPGA at 100Hz any time it is installed.  In summary, the FPGA can only be
reloaded when the touchscreen driver, ts4800ctl, and any other processes that
try to talk to the FPGA, are not running.

