TS-7500:
 * Revision history:
 * 0 - Initial release
 * 1 - Added 5-bit PLL phase shift register for SPI.  (Needed for +80C)
 * 2 - Improved GPIO performance by putting the syscon block on its own
 *     clock domain synchronous to the SPI clock.  Also updated SPI controller.
 * 3 - XUART channel #0 RX line was hooked up incorrectly.
 * 4 - Added improved SPI controller and extra CS2# and CS3#
 *     optional CAN controller added
 *     moved to 16Kbyte bootrom
 *     fixed IRQ output
 * 5 - Updated SPI controller with extra slower speeds (1.2Mhz) and CS#
 *     bit in control reg.  Fixed int28 to always be high (fixes USB 
 *     slave issue)

TS-7550:
 * Revision history:
 * 0 - Initial release
 * 1 - Connected SPI controller CS#2 and #3 to override DIO37 and DIO38
 *     SPI controller modded to allow running at lower clock rates
 *     Fixed XUART IRQ output on CPU GPIO A0 and A1.
 *     Output 32khz clock for CPU
 * 2 - SPI controller speed to 1.2Mhz and CS# bit in control reg.  Int28
 *     IRQ set high (fixes USB slave device issue)
 * 3 - CAN was always overriding pin 23/24 even if it wasn't enabled
 * 4 - Bootrom update (not applicable to opencore)

TS-7552:
 * Revision history:
 * 0 - Initial release
 * 1 - Fixed CAN controller

TS-7553:
 * Revision history:
 * 0 - Initial release
 * 1 - Bootrom update bump, fixed CAN controller, allow CAN to optimize out
 *              XUART4-7 to 26-pin header, bug 151 fix (RTC drift)
 * 2 - Mute RS485 when transmitting

TS-4500:
 * Revision history:
 * 0 - Initial release
 * 1 - Added another bit to SPI speed to allow lower speeds (1.2Mhz),
 *     fixed DIO pins, fixed ethernet LEDs, added CAN enable reg bit.
 * 2 - Fix CAN clock enable/disable.
 * 3 - Add TS-8510 full-duplex RS485 (RS422) enable bit to syscon.  Also
 *     add RS422 enable bit for all the other macrocontroller base boards.
 *     Update bootrom to Dec 1
 * 4 - Memwindow and muxbus support added
